1. Field of the Invention
This disclosure relates generally to the field of semiconductor devices, and more particularly, to improved mirror mode operation of semiconductor memory devices.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional memory system 100 having several memory modules. The memory system 100 includes two memory modules 105, 110. Each memory module 105, 110 includes several dynamic random access memory (DRAM) devices 120 and a control/address (C/A) buffer 125. The DRAM devices 120 and the C/A buffer 125 are mounted on a module board. The DRAM devices 120 and C/A buffers on each of the memory modules 105, 110 receive signals transferred from a controller 115 through a socket/connector (not shown) mounted on the mother board/module board. A data (DQ) bus and a clock (CLK) bus on the motherboard are commonly connected with the DRAM devices 120 on each of the memory modules 105, 110. The DRAM devices 120 are stub loads for the DQ and CLK busses, thus the configuration illustrated in FIG. 1 is sometimes referred to as a “stub-bus” configuration. Although only one side of the memory modules 105, 110 are illustrated in FIG. 1, there may be other DRAM devices 120 and/or C/A buffers 125 mounted on the other side. In this case the memory modules 105, 110 are commonly known as Dual Inline Memory Modules (DIMMs).
FIG. 2 is a schematic diagram illustrating two integrated circuits in a conventional mirrored pair arrangement. The external signals that are applied to the bonding pads of the device 310 are symmetrical to those applied to the bonding pads of the device 320. Depending on the selection logic SEL that is applied to the MUX 315, 325 of each of the integrated circuits, appropriate internal switching configurations may be established. For example, as shown in FIG. 2, the signals A2, A10, /RAS, CK, /CK, /CS, A9, and A5 may be assigned to pads 340, 345, 350, 355, 360, 365, 370, 375 of the normal device 310. The mirrored device 320, on the other hand, may have the signals A5, A9, /CS, /CK, CK, /RAS, A10, and A2 assigned to respective pads 340-375.
FIG. 3 is a schematic diagram illustrating a memory controller coupled to a normal package and to a mirrored package that are in a paired configuration according to the conventional art. The memory controller 400 generates exemplary signals A, . . . , B, DQ1, . . . , DQ7. Mirrored package 410 is arranged “back-to-back” with normal package 420 as was described above in FIG. 2, thus adjacent pins of the packages 410, 420 may be tied together as indicated in FIG. 3. In the normal package 420, the pins for A, B, DQ1, and DQ7 signals are assigned to receive the signals A, B, DQ1, and DQ7, respectively. Herein, the pins for A, B, DQ1, and DQ7 signals are respectively connected to the corresponding pads for A, B, DQ1, and DQ7 signals which is located in the devices 410, 420 (not shown). However, in the mirrored package 410, the pins for A, B, DQ1, and DQ7 signals are assigned to receive the signals B, A, DQ7, and DQ1, respectively.
FIG. 4 is a schematic diagram illustrating the pin arrangement of a conventional DIMM having a number of memory devices mounted on the module board. There are a number of memory devices 10-1, 10-2, . . . , 10-n mounted on the front side 10 of the memory module. There are also a number of memory devices 20-1, 20-2, . . . , 20-n mounted on a rear side 20 of the memory module.
Each memory device 10-1, . . . 10-n, 20-1, . . . , 20-n, receives common power signals (power), common command signals (com), common address signals (add), non-shared command signals (ncom1, ncom2,), and common data signals (data) from a memory controller. Generally, power signals may include a power supply signal (VCC) or a ground potential signal (VSS). The command signals (com) may include a number of signals such as a clock signal (CK) a row address strobe signal (RASB), a column address signal (CASB), a write enable signal (WEB), a clock enable signal (CKE), etc.
Furthermore, each of the memory devices 10-1, . . . , 10-n on the front side 10 of the memory module receives a “non-shared” command signal ncom2. Similarly, each of the memory devices 20-1, . . . , 20-n on the rear side 20 of the memory module receives a “non-shared” command signal ncom1. In other words, the non-shared command signal ncom1 is commonly applied to all memory devices on the rear side 20 of the memory module and the non-shared command signal ncom2 is commonly applied to all memory devices on the front side 10 of the memory module. For purposes of this disclosure, the term “non-shared” is interpreted in its broadest sense to describe any signal that is not commonly shared among all the memory devices on the memory module.
The power signal (power) pins, command signal (corn) pins, address signal pins (add), and data signal pins (data) are commonly connected to all memory devices mounted on the module board. However, since each of the memory devices is configured in a normal pin arrangement, the pin arrangement on the front side 10 if the memory module is asymmetrically arranged compared to the pin arrangement on the rear side 20 of the memory module. Because of this, the shared signal lines (power, corn, add, data) must be separated on the module board.
For example, the number 1 pin of memory device 10-1 and the number 1 pin of memory device 20-1 are not located directly adjacent to the other, rather each is offset to the right or left with respect to the other. Consequently, the signal lines must be separated in order to supply the signal to both of the pins. One of the signal leads will necessarily be shorter than the other, which results in a “short stub” load that may cause unwanted reflections and degrade signal quality, especially at high frequency operation.
FIG. 5 is a schematic diagram illustrating a conventional memory device 600 capable of a mirror mode function. The device 600 receives a number of external signals such as power signals (VCC, VREF, GND), non-shared command signals (NCOM), command signals (COM), address signals (ADD), and data signals (DATA) at external pins. The external signals mentioned above appear at corresponding pads PVCC, PVREF, PGND, PNCOM, PCOM, PADD, and PDATA.
The memory device 600 operates in normal mode or mirror mode depending on the signals that are applied to the switching circuit 610. When the switching circuit 610 is connected to the power supply source pad PVCC via the bonding option pad 600-1, the memory device 600 operates in mirror mode. That is, the switching circuit 610 switches an arrangement of input signals inputted from variable external terminals to a different type arrangement. For example, the input signals applied to the command and address pads (PNCOM, PCOM, and PADD) are respectively transferred to a corresponding number of internal data signals (idata) rather than a corresponding number of internal command and address signals (income, icom, iadd).
On the other hand, when the switching circuit 610 is connected to the ground potential signal (PGND) pad through the bonding option pad 600-2, the memory device operates in normal mode. That is, the input signals of the command and address pads (PNCOM, PCOM, and PADD) are respectively transferred to internal command signals (income, icom) and internal address signals (iadd) without translation to other internal signals. In normal mode, the input signals of the data signal pads (PDATA) are also respectively transferred to a number of corresponding internal data signals (idata).
In order to operate the conventional memory device 600 in mirror or normal mode as described above, it is frequently necessary to increase the size of the device to accommodate additional bonding option pads (such as 600-1, 600-2) or pins. This translates into an increased manufacturing cost.
Embodiments of the invention address these and other disadvantages of the conventional art.